High performance microprocessors use a variety of memory management techniques to map a logical address to a physical address space. These techniques includes features, such as segmentation and paging, which allow memory to be managed efficiently and reliably. The address generation unit (AGU) is a key component of the memory management block of high performance microprocessors.
AGUs within high performance microprocessors are used to compute the effective address of the locations being addressed in memory. This operation is defined as:Effective Address=(segment+displacement)+base+(index*scale)   (1)
A variety of addressing modes can be implemented by choosing appropriate values for each of the five address components provided in Equation (1). Regardless of the selection of values for the various components of the effective address, an AGU requires, for example, 32-bit and 64-bit addition to compute the effective address. Accordingly, effective address computation is a performance critical, single cycle operation that requires a high performance AGU.
Hence, AGUs in microprocessors require a high performance adder core to compute the effective addresses of memory locations being accessed. Unfortunately, best known methods for implementing adder cores use non-optimal fan outs and an expensive carry-merge tree structure, resulting in high wiring complexity and thus increased area and power. As a result, the activity of the AGU can create thermal hotspots and sharp temperature gradients in the execution core of high performance microprocessors that may considerably affect circuit reliability and increase cooling costs. The presence of multiple execution engines in current processors, such as chip multiprocessors (CMP) further aggravates the problem.